1. Technical Field
The present invention generally relates to dynamic logic gates, and more particularly to logic gates with short evaluation times.
2. Description of Related Art
Dynamic logic circuits are well known in the art. Dynamic Random Access Memory (RAM) arrays use dynamic logic to decrease device count, and microprocessors use dynamic logic to decrease device count and increase speed. Referred to as domino circuits, clocked dynamic logic performs evaluation and storage functions in VLSI (Very Large Scale Integration) designs and is a preferred topology in microprocessors and memory devices designed for high speed operation.
In order to achieve high speed in dynamic logic circuits, control signals are used to precharge nodes in the circuits to known values, typically at or near one of the power supply rails. There is typically a precharge state and then an evaluation state in which the logic evaluation takes place.
Several domino circuit families are in widespread use today. These can include footed types, where the logic ladders are disconnected from one rail during the precharge phase, or unfooted designs. They can also be single rail or dual rail. Dual rail designs use differential ladders and provide complementary outputs. Another topology is the pseudo-clocked topology, where one of the logic inputs is used to control the evaluation state.
In a logic gate, evaluation of the AND-OR logical product-sum function is typically provided by ladders of input transistors, where serial connection of transistor sources and drains provide an AND function. By way of example, referring to FIG. 1, NFETS QF4, QF5 and QF6 form one such input ladder. Unless all of these devices are on, the ladder does not lower the voltage at node n1. Parallel connection of these AND ladders provides the OR function. NFETS QF3, QF12 and QF13 provide a second AND ladder. Both of these ladders must be inactive for the voltage at node n1 to remain precharged during an evaluation cycle, therefore the parallel combination accomplishes an OR function. As more OR terms are added, more parallel switching ladders add capacitive loading to the evaluation node. As more AND terms are added, the transistor areas have to be increased to maintain the same resistive path to the rail. Footing transistors such as QF11 likewise have to be increased in size as more AND terms are added. If the resistive path increases, the evaluation speed of the gate will suffer and the switching ability of the AND ladder will be reduced due to higher voltage at the node at the top of the AND ladder. Again referring to FIG. 1, by way of example, device QF6 has a higher turn on threshold than QF4, since the voltage at the source of QF6 is higher by the potential across QF4 and QF5. This affects the switching speed at input a, which sets a practical limitation on the number of AND terms which can be obtained in a ladder for a fixed transistor area. Increasing the area of the transistors also increases the capacitive loading at the evaluation node. This capacitive loading increases the evaluation time of the dynamic logic gate.
It would, therefore, be desirable to provide a dynamic logic circuit with reduced evaluation time, so that more AND and OR terms can be added to a gate for a desired evaluation speed.